1. Field of the Invention
The present invention relates to a driver circuit, and particularly to a body bias variable driver circuit for implementing operation at a low source voltage.
This application is a counterpart of Japanese Patent Application, Serial Number 006093/2000, filed Jan. 11, 2000, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
A circuit disclosed in the following reference has heretofore been proposed as an SOI (Silicon On Insulator). driver circuit for controlling a substrate voltage.
xe2x80x9cBody Bias Variable SOI-CMOS Driver Circuitxe2x80x9d, by Yoshiki Wada et al; Mitsubishi Electric Corp., S. (Signal)-L.(Learning) Technical Report of IEICE, ICD97-45, p. 23-29, 1997
A description will now be made of the body bias variable SOI-CMOS driver circuit (hereinafter abbreviated as xe2x80x9cdriver circuitxe2x80x9d disclosed in the above-described reference. FIG. 8 is a circuit diagram of the driver circuit disclosed in the above-described reference. The driver circuit comprises an inverter circuit A, a substrate voltage supply circuit B and an inverter circuit C. The substrate voltage supply circuit B is electrically connected to the inverter circuit A and the inverter circuit C.
The inverter circuit A comprises a PMOS transistor 802 and an NMOS transistor 803.
The PMOS transistor and NMOS transistor will now be described. The PMOS transistor is an abbreviation for xe2x80x98P channel MOS transistorxe2x80x99 and is comprised of a control electrode, a first electrode, and a second electrode. The first electrode of the PMOS transistor serves as a source or drain electrode, and the second electrode thereof serves as a drain or source electrode. When a reference voltage GND (also called xe2x80x9cground voltage GNDxe2x80x9d; hereinafter abbreviated as xe2x80x9cvoltage GNDxe2x80x9d is applied to the control electrode of the PMOS transistor, the PMOS transistor is brought to a conducting state. On the other hand, when a source voltage VDD (also called xe2x80x9cdrive voltage VDDxe2x80x9d; hereinafter abbreviated as xe2x80x9cvoltage VDDxe2x80x9d is applied to the control electrode of the PMOS transistor, the PMOS transistor is brought to a non-conducting state. Next, the NMOS transistor is an abbreviation for xe2x80x98N channel MOS transistorxe2x80x99 and comprises a control electrode, a first electrode and a second electrode. The first electrode of the NMOS transistor serves as a source or drain electrode, and the second electrode thereof serves as a drain or source electrode. When the voltage VDD is applied to the control electrode of the NMOS transistor,the NMOS transistor is brought to the conducting state. On the other hand, when the voltage GND is applied to the control electrode of the NMOS transistor, the NMOS transistor is brought to the non-conducting state. Incidentally, a period during which each of the PMOS transistor and the NMOS transistor changes from the non-conducting state to the conducting state, is called an xe2x80x9cactive periodxe2x80x9d and a period other than that is called a xe2x80x9cstatic periodxe2x80x9d in the subsequent description.
In the inverter circuit A, the control electrode of the PMOS transistor 802 is electrically connected to a node 801, the first electrode thereof is supplied with the voltage VDD, and the second electrode thereof is electrically connected to a node 804. Further, the control electrode of the NMOS transistor 803 is electrically connected to the node 801, the first electrode thereof is supplied with the voltage GND, and the second electrode thereof is electrically connected to the node 804.
The substrate voltage supply circuit B comprises two PMOS transistors 805 and 806 and two NMOS transistors 807 and 808.
The voltage GND is applied to a control electrode of the PMOS transistor 805, the voltage VDD is applied to a first electrode thereof. Further, a second electrode of the PMOS transistor 805 is electrically connected to a node BP. In the substrate voltage supply circuit B, the voltage GND is always applied to the control electrode of the PMOS transistor 805 so that the PMOS transistor 805 is always kept in conduction. Thus, the PMOS transistor 805 is used as resistance means interposed between the node BP and the voltage VDD. A control electrode of the PMOS transistor 806 is electrically connected to a node 809, a first electrode thereof is electrically connected to the node BP, and a second electrode thereof is electrically connected to the node 804. A substrate for the PMOS transistor 806 and the node BP are now connected to each other, whereby the voltage applied to the. substrate of the PMOS transistor 806 depends on a voltage applied to the node BP.
The voltage VDD is applied to a control electrode of the NMOS transistor 807, a first electrode thereof is supplied with the voltage GND, and a second electrode thereof is electrically connected to a node BN.
In the substrate voltage supply circuit B, the voltage VDD is applied to the control electrode of the NMOS transistor 807 at all times so that the NMOS transistor 807 is always kept in conduction. Thus, the NMOS transistor 807 is utilized as resistance means interposed between the node BN and the voltage GND. A control electrode of the NMOS transistor 808 is electrically connected to the node 809, a first electrode thereof is electrically connected to the node BN, and a second electrode thereof is electrically connected to the node 804. A substrate for the NMOS transistor 808 is electrically connected to the node BN here, so that a voltage applied to the substrate of the NMOS transistor 808 depends on the voltage applied to the node BN.
The inverter circuit C comprises a PMOS transistor 810 and an NMOS transistor 811. A control electrode of the PMOS transistor 810 is electrically connected to the node 804, a first electrode thereof is supplied with the voltage VDD, and a second electrode thereof is electrically connected to the node 809. Further, a control electrode of the NMOS transistor 811 is electrically connected to the node 804, a first electrode thereof is supplied with the voltage GND, and a second electrode thereof is electrically connected to the node 809. A substrate for the PMOS transistor 810 is electrically connected to the node BP, whereas a substrate for the NMOS transistor 811 is electrically connected to the node BN.
The operation of the driver circuit described in the above-described reference will next be explained with reference to FIGS. 8 and 9. FIG. 9 shows the result of simulation of the driver circuit. FIG. 9(a) is a timing chart showing waveforms at the nodes 804 and 809. FIG. 9(b) is a timing chart showing waveforms at the nodes BP and BN.
Now consider where the voltage GND is first applied to the node 801 at a time T1. In doing so, the NMOS transistor 803 is brought into non-conduction and the PMOS transistor 802 is brought into conduction. Thus, the node 804 is brought to the voltage VDD since the PMOS transistor 802 is kept in conduction.
Since the voltage VDD is applied to the node 804, the PMOS transistor 810 is brought into non-conduction and the NMOS transistor 811 is brought into conduction. Thus, since the NMOS transistor 811 is kept in conduction, the node 809 assumes the voltage GND.
Since the voltage GND is applied to the node 809, the NMOS transistor 808 is brought to the non-conducting state and the PMOS transistor 806 is brought to the conducting state. Since the NMOS transistor 808 is kept in non-conduction, the node BN is maintained at the voltage GND. Since the NMOS transistor 807 is kept in conduction, the voltage GND is applied to the substrates for the NMOS transistor 808 and the NMOS transistor 811. On the other hand, since the PMOS transistor 806 is kept in conduction and the PMOS transistor 805 is kept in conduction, the voltage VDD is applied to the node 804. Incidentally, since the PMOS transistor 805 is kept in conduction, the voltage VDD is applied to the substrates for the PMOS transistors 806 and 810
Assume that the voltage VDD is next applied to the node 801 between times T1 and T2. In doing so, the voltage applied to the node 801 changes from the xe2x80x9cvoltage GND at the time T1xe2x80x9d to the xe2x80x9cvoltage VDDxe2x80x9d, so that the NMOS transistor 803 is brought to the conducting state and the PMOS transistor 802 is brought to the non-conducting state. Thus, since the NMOS transistor 803 is kept in conduction, the voltage at the node 804 is changed to the voltage GND.
Owing to the change of the voltage at the node 804 to the voltage GND, the PMOS transistor 810 is brought into conduction and the NMOS transistor 811 is brought into non-conduction. Since the PMOS transistor 810 is kept in conduction, the voltage at the node 809 is changed to the voltage VDD.
A slight time is required to perform processing in the inverter circuit C by the time the voltage at the node 809 changes from the xe2x80x9cvoltage GNDxe2x80x9d to the xe2x80x9cvoltage VDDxe2x80x9d after the voltage at the node 804 has been changed from the xe2x80x9cvoltage VDDxe2x80x9d to the xe2x80x9cvoltage GNDxe2x80x9d. Thus, the PMOS transistor 806 is maintained in the conducting state. As a result, a time zone exists in which the PMOS transistor 805, PMOS transistor 806 and NMOS transistor 803 are kept in conduction. Thus, a flow of current occurs over a channel or path extending in order of the xe2x80x9cvoltage VDD-xe2x86x92PMOS transistor 805-xe2x86x92PMOS transistor 806-xe2x86x92NMOS transistor 803-xe2x86x92voltage GNDxe2x80x9d (this will hereinafter be called xe2x80x9ccurrent path is producedxe2x80x9d. Owing to such path generation, the voltage at the node BP to which the voltage VDD is applied, gradually drops. A drop in voltage of the node BP is terminated when the voltage at the node 809 is changed to the voltage VDD and the PMOS transistor 806 is brought to the non-conducting state. Thereafter, the voltage VDD is applied to the node BP through the PMOS transistor 805 kept in conduction at all times, whereby the voltage applied to the node BP gradually rises to the voltage VDD.
Assume that the voltage GND is next applied to the node 801 between times T3 and T4. The state of each circuit of the driver circuit disclosed in the reference at the time T3 is identical to that at the time T2 described in the above. In doing so, the voltage applied to the node 801 changes from the xe2x80x9cvoltage VDD at the time T3 to the xe2x80x9cvoltage GNDxe2x80x9d, so that the PMOS transistor 802 is brought into conduction and the NMOS transistor 803 is brought into non-conduction. Thus, since the PMOS transistor 802 is kept in conduction, the voltage at the node 804 is changed to the voltage VDD.
Since the voltage at the node 804 reaches the voltage VDD, the NMOS transistor 811 is brought into conduction and the PMOS transistor 810 is brought into non-conduction. Since the NMOS transistor 811 is kept in conduction, the voltage at the node 809 is changed to the voltage GND.
A slight time is required to perform processing in the inverter circuit C by the time the voltage at the node 809 changes from the xe2x80x9cvoltage VDDxe2x80x9d to the xe2x80x9cvoltage GNDxe2x80x9d after the voltage at the node 804 has been changed from the xe2x80x9cvoltage GNDxe2x80x9d to the xe2x80x9cvoltage VDDxe2x80x9d. Thus, the NMOS transistor 808 is maintained in the conducting state. As a result, a time zone exists in which the PMOS transistor 802, NMOS transistor 808 and NMOS transistor 807 are kept in conduction. Thus, a current path is generated over a channel or path extending in order of the xe2x80x9cvoltage VDD-xe2x86x92PMOS transistor 802-xe2x86x92NMOS transistor 808-xe2x86x92NMOS transistor 807-xe2x86x92voltage GNDxe2x80x9d. Owing to such generation, the voltage at the node BN to which the voltage GND is applied, gradually rises. A rise in voltage of the node BN is terminated when the voltage at the node 809 is changed to the voltage GND and the NMOS transistor 808 is brought to the non-conducting state. Thereafter, the voltage GND is applied to the node BN through the NMOS transistor 807 kept in conduction at all times, whereby the voltage at the node BN gradually drops to the voltage GND.
As described above, when the voltage applied to the node 801 changes, the conventional driver circuit generates the two kinds of current paths according to the applied voltage.
A description will first be made of the meaning that the conventional driver circuit generates the current path in order of the xe2x80x9cvoltage VDD-xe2x86x92PMOS transistor 805-xe2x86x92PMOS transistor 806-xe2x86x92NMOS transistor 803-xe2x86x92voltage GNDxe2x80x9d. The conventional driver circuit generates the current path so as to reduce the voltage applied to the node BP. Owing to the reduction in the voltage applied to the node BP, the conventional driver circuit lowers the voltage applied to the substrate for the PMOS transistor 810. Owing to the reduction in the substrate voltage of the PMOS transistor 810, the conventional driver circuit reduces a threshold voltage of the PMOS transistor 810 and increases a driving force of the PMOS transistor 810. Thus, the conventional driver circuit can be operated at high speed even when the PMOS transistor 810 constituting the inverter circuit C is placed under the low source voltage.
A description will next be made of the meaning that the conventional driver circuit generates the current path in order of the voltage VDD-xe2x86x92PMOS transistor 802-xe2x86x92NMOS transistor 808-xe2x86x92NMOS transistor 807-xe2x86x92voltage GNDxe2x80x9d. The conventional driver circuit generates the current path to thereby increase the voltage applied to the node BN. Owing to the increase in the voltage applied to the node BN, the conventional driver circuit raises the voltage applied to the substrate for the NMOS transistor 811 connected to the node BN. With the increase in the substrate voltage of the NMOS transistor 811, the conventional driver circuit reduces a threshold voltage of the NMOS transistor 811 and raises a driving force of the NMOS transistor 811. Thus, the conventional driver circuit can be operated at high speed even when the NMOS transistor 811 constituting the inverter circuit C is placed under the low source voltage.
In the conventional driver circuit, however, a drop in the voltage applied to the node BP due to the current path generated over the path extending in order of the xe2x80x9cvoltage VDD-xe2x86x92PMOS transistor 805-xe2x86x92PMOS transistor 806-xe2x86x92NMOS transistor 803-xe2x86x92voltage GNDxe2x80x9d, is terminated when the voltage VDD is applied to the node 809 and the PMOS transistor 806 is brought into non-conduction. Thereafter, the voltage VDD is applied to the node BP through the PMOS transistor 805 kept in conduction at all times, so that the voltage applied to the node BP gradually rises to the voltage VDD. Thus, the voltage applied to the node BP is kept in a low state as compared with the voltage VDD until it is returned to the voltage VDD through the PMOS transistor 805. Since the voltage applied to the node BP results in the voltage applied to the substrate for the PMOS transistor 810, the threshold voltage of the PMOS transistor 810 is brought to a low state even during the static period. Thus, when the threshold voltage is kept in the low state during the static period, a sub-threshold leakage current, which flows in a channel direction of the PMOS transistor 810, becomes great and hence power consumption cannot be reduced to a sufficient degree. Further, a rise in the voltage applied to the node BN due to the current path extending in order of the xe2x80x9cvoltage VDD-xe2x86x92PMOS transistor 802-xe2x86x92NMOS transistor 808-xe2x86x92NMOS transistor 807-xe2x86x92voltage GNDxe2x80x9d is terminated when the voltage GND is applied to the node 809 and the NMOS transistor 808 is brought into non-conduction. Thereafter, the voltage GND is applied to the node BN through the NMOS transistor 807 kept in conduction at all times, so that the voltage applied to the node BN gradually drops. Thus, the voltage applied to the node BN is kept in a state higher than the voltage GND until it is returned to the voltage GND through the NMOS transistor 807. Here the voltage applied to the node BN is brought to the substrate voltage of the NMOS transistor 811, so that the threshold voltage of the NMOS transistor 811 is brought to a low state even during the static period. Thus, when the threshold voltage is kept in the low state during the static period, a sub-threshold leakage current, which flows in a channel direction of the NMOS transistor 811, becomes great, so that power consumption cannot be sufficiently reduced.
With the foregoing problems in view, it is therefore an object of the present invention to provide a driver circuit comprising a first inverter circuit for inverting an input voltage and supplying a first inverted voltage therefrom, a second inverter circuit which has a first conduction type transistor and a second conduction type transistor different from the first conduction type transistor and which inverts the first inverted voltage and supplies a second inverted voltage therefrom, a substrate voltage supply circuit for supplying voltages to a substrate for the first conduction type transistor and a substrate for the second conduction type transistor according to the second inverted voltage respectively, and a first substrate voltage control circuit for adjusting the voltage applied to the substrate for the first conduction type transistor according to the second inverted voltage.
It is another object of the present invention to provide a driver circuit comprising a first inverter circuit for inverting an input voltage and supplying a first inverted voltage therefrom, a second inverter circuit which has a first conduction type transistor and a second conduction type transistor different from the first conduction type transistor and which inverts the first inverted voltage and supplies a second inverted voltage therefrom, a substrate voltage supply circuit for supplying voltages to a substrate for the first conduction type transistor and a substrate for the second conduction type transistor according to the second inverted voltage respectively, and a second substrate voltage control circuit for adjusting the voltage applied to the substrate for the second conduction type transistor according to the second inverted voltage.
It is a further object of the present invention to provide a driver circuit comprising a first inverter circuit for inverting an input voltage and supplying a first inverted voltage therefrom, a second inverter circuit which includes a first conduction type transistor and a second conduction type transistor different from the first conduction type transistor and which inverts the first inverted voltage and supplies a second inverted voltage therefrom, a substrate voltage supply circuit for supplying voltages to a substrate for the first conduction type transistor and a substrate for the second conduction type transistor according to the second inverted voltage respectively, and a third substrate voltage control circuit for adjusting the voltages applied to the substrates for the first and second conduction type transistors according to the second inverted voltage.
Typical ones of various inventions of the present inventions have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.